Roger Chamberlain's Publications

• Joseph M. Lancaster, Joseph G. Wingbermuehle, Jonathan C. Beard, and Roger D. Chamberlain, "Crossing Boundaries in TimeTrial: Monitoring Communications Across Architecturally Diverse Computing Platforms," in Proc. of Ninth IEEE/IFIP International Conference on Embedded and Ubiquitous Computing (EUC), October 2011, pp. 280-287.

• Lin Ma, Roger D. Chamberlain, Jeremy D. Buhler, and Mark A. Franklin, "Bloom Filter Performance on Graphics Engines," in Proc. of 40th International Conference on Parallel Processing (ICPP), September 2011, pp. 522-531.

• Joseph M. Lancaster, E. F. Berkley Shands, Jeremy D. Buhler, and Roger D. Chamberlain, "TimeTrial: A Low-Impact Performance Profiler for Streaming Data Applications," in Proc. of 22nd IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP), September 2011, pp. 69-76.

• Shobana Padmanabhan, Yixin Chen, and Roger D. Chamberlain, "Optimal Design-Space Exploration of Streaming Applications," in Proc. of 22nd IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP), September 2011, pp. 227-230.

• Joseph M. Lancaster, Joseph G. Wingbermuehle, and Roger D. Chamberlain, "Asking for Performance: Exploiting Developer Intuition to Guide Instrumentation with TimeTrial," in Proc. of 13th International Conference on High Performance Computing and Communications (HPCC), September 2011.

• John Meier, Christopher Gill, and Roger D. Chamberlain, "Towards More Effective Spectrum Use Based on Memory Allocation Models," in Proc. of 35th IEEE Computer Software and Applications Conference (COMPSAC), July 2011, pp. 426-435.

• Todd Sproull and Roger D. Chamberlain, "Evaluation of the Placement of Network Services," in Proc. of 2011 International Conference on Internet Computing (ICOMP), July 2011, pp. 10-16.

• Michael J. Hall, Viktor Gruev, and Roger D. Chamberlain, "Noise Analysis of a Current-Mode Read Circuit for Sensing Magnetic Tunnel Junction Resistance," in Proc. of IEEE International Symposium on Circuits and Systems (ISCAS), May 2011, pp. 1816-1819.

• Narayan Ganesan, Roger D. Chamberlain, Jeremy Buhler, and Michela Taufer, "Rolling Partial Prefix-Sums To Speedup Evaluation of Uniform and Affine Recurrence Equations," in Proc. of SPIE Defense, Security, and Sensing Conference, April 2011.

• Narayan Ganesan, Roger D. Chamberlain, Jeremy Buhler, and Michela Taufer, "Accelerating HMMER on GPUs by Implementing Hybrid Data and Task Parallelism," in Proc. of ACM International Conference on Bioinformatics and Computational Biology (ACM-BCB), August 2010, pp. 418-421.

• Rahav Dor, Joseph M. Lancaster, Mark A. Franklin, Jeremy Buhler, and Roger D. Chamberlain, "Using Queuing Theory to Model Streaming Applications," in Proc. of 2010 Symposium on Application Accelerators in High Performance Computing (SAAHPC), July 2010.

• Joseph M. Lancaster and Roger D. Chamberlain, "Crossing Timezones in the TimeTrial Performance Monitor," in Proc. of 2010 Symposium on Application Accelerators in High Performance Computing (SAAHPC), July 2010.

• Shobana Padmanabhan, Yixin Chen, and Roger D. Chamberlain, "Design-space Optimization for Automatic Acceleration of Streaming Applications," in Proc. of 2010 Symposium on Application Accelerators in High Performance Computing (SAAHPC), July 2010.

• Roger D. Chamberlain and Joseph M. Lancaster, "Better Languages for More Effective Designing," in Proc. of 2010 International Conference on Engineering of Reconfigurable Systems & Algorithms (ERSA), July 2010.

• Todd Sproull and Roger D. Chamberlain, "Distributed Algorithms for the Placement of Network Services," in Proc. of 2010 International Conference on Internet Computing (ICOMP), July 2010.

• Arpith C. Jacob, Jeremy D. Buhler, and Roger D. Chamberlain, "Design of throughput-optimized arrays from recurrence abstractions," in Proc. of 21st IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP), July 2010, pp. 133-140.

• Peng Li, Kunal Agrawal, Jeremy Buhler, Roger D. Chamberlain, and Joseph M. Lancaster, "Deadlock-avoidance for Streaming Applications with Split-Join Structure: Two Case Studies," in Proc. of 21st IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP), July 2010, pp. 333-336.

• Peng Li, Kunal Agrawal, Jeremy Buhler, and Roger D. Chamberlain, "Deadlock Avoidance for Streaming Computation with Filtering," in Proc. of 22nd ACM Symposium on Parallelism in Algorithms and Architectures (SPAA), June 2010, pp. 243-252.

• Arpith C. Jacob, Jeremy D. Buhler, and Roger D. Chamberlain, "Rapid RNA Folding: Analysis and Acceleration of the Zuker Recurrence," in Proc. of 18th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), May 2010, pp. 87-94.

• Ross Sowell, Christopher Gill, Roger D. Chamberlain, Cindy Grimm, Kenneth J. Goldman and Mark Tranel, "The active-learning transformation: a case study in software development and systems software courses," Journal of Computing Sciences in Colleges, 25(5):165-172, May 2010.

• Roger D. Chamberlain, Jeremy Buhler, Mark A. Franklin, and James H. Buckley, "Application-guided Tool Development for Architecturally Diverse Computation," in Proc. of Symposium on Applied Computing (SAC), March 2010, pp. 496-501.

• Roger D. Chamberlain, Mark A. Franklin, Eric J. Tyson, James H. Buckley, Jeremy Buhler, Greg Galloway, Saurabh Gayen, Michael Hall, E.F. Berkley Shands, and Naveen Singla, "Auto-Pipe: Streaming Applications on Architecturally Diverse Systems," Computer, 43(3):42-49, March 2010.

• Roger D. Chamberlain and Narayan Ganesan, "Sorting on Architecturally Diverse Computer Systems," in Proc. of Third Int'l Workshop on High-Performance Reconfigurable Computing Technology and Applications (HPRCTA), November 2009 (associated with Supercomputing'09).

• Octav Chipara, Christopher Brooks, Sangeeta Bhattacharya, Chenyang Lu, Roger D. Chamberlain, Gruia-Catalin Roman, and Thomas C. Bailey, "Reliable Real-time Clinical Monitoring Using Sensor Network Technology," in American Medical Informatics Association (AMIA) Annual Symposium Proceedings, November 2009.

• Joseph M. Lancaster, Jeremy D. Buhler, and Roger D. Chamberlain, "Efficient Runtime Performance Monitoring of FPGA-based Applications," in Proc. of 22nd IEEE Int'l System-on-Chip Conf. (SoCC), September 2009, pp. 23-28.

• Arpith C. Jacob, Jeremy D. Buhler, and Roger D. Chamberlain, "Optimal Runtime Reconfiguration Strategies for Systolic Arrays," in Proc. of 19th Int'l Conf. on Field Programmable Logic and Applications (FPL), August 2009, pp.162-167.

• Narayan Ganesan, Roger D. Chamberlain, and Jeremy Buhler, "Acceleration of Binomial Options Pricing via Parallelizing along Time-axis on a GPU," in Proc. of Symp. on Application Accelerators in High Performance Computing (SPAAHPC), July 2009.

• Joseph Lancaster, Jeremy Buhler, and Roger D. Chamberlain, "Acceleration of Ungapped Extension in Mercury BLAST," Microprocessors and Microsystems, 33(4):281-289, June 2009.

• Michael Hall, Albrecht Jander, Roger D. Chamberlain, and Pallavi Dhagat, "Globally Clocked Magnetic Logic Circuits," in Digest of Int'l Magnetics Conference (Intermag), May 2009.

• Naveen Singla, Michael Hall, Berkley Shands, and Roger D. Chamberlain, "Financial Monte Carlo Simulation on Architecturally Diverse Systems," in Proc. of Workshop on High Performance Computational Finance, November 2008 (associated with Supercomputing'08).

• Eric J. Tyson, James Buckley, Mark A. Franklin, and Roger D. Chamberlain, "Acceleration of atmospheric Cherenkov telescope signal processing to real-time speed with the Auto-Pipe design system," Nuclear Instruments and Methods in Physics Research A, 585(2):474-479, October 2008.

• Arpith Jacob, Joseph Lancaster, Jeremy Buhler, Brandon Harris, and Roger D. Chamberlain, "Mercury BLASTP: Accelerating Protein Sequence Alignment," ACM Trans. on Reconfigurable Technology and Systems, 1(2):1-44, June 2008.

• Roger D. Chamberlain, Joseph M. Lancaster, and Ron K. Cytron, "Visions for Application Development on Hybrid Computing Systems," Parallel Computing, 34(4-5):201-216, May 2008.

• Praveen Krishnamurthy and Roger D. Chamberlain, "Analytic Performance Models for Bounded Queueing Systems," in Proc. of Workshop on Advances of Parallel and Distributed Computing Models (APDCM), April 2008 (associated with IPDPS).

• Joseph Lancaster, Ron Cytron, and Roger D. Chamberlain, "Understanding the Performance of Streaming Applications Deployed on Hybrid Systems," in Proc. of Next Generation Software Workshop (NGS), April 2008 (associated with IPDPS).

• Saurabh Gayen, Mark A. Franklin, Eric J. Tyson, Roger D. Chamberlain, "Simulation of Streaming Applications on Multicore Systems," in Proc. of 3rd Workshop on Software Tools for MultiCore Systems (STMCS), April 2008.

• Roger D. Chamberlain, Eric J. Tyson, Saurabh Gayen, Mark A. Franklin, Jeremy Buhler, Patrick Crowley, and James Buckley, "Application Development on Hybrid Systems," in Proc. of ACM/IEEE Supercomputing Conf. (SC07), November 2007.

• Praveen Krishnamurthy, Jeremy Buhler, Roger D. Chamberlain, Mark A. Franklin, Kwame Gyang, Arpith Jacob, and Joseph Lancaster, "Biosequence Similarity Search on the Mercury System," Journal of VLSI Signal Processing, 49(1):101-121, October 2007.

• Roger D. Chamberlain and Berkley Shands, "Direct-Attached Disk Subsystem Performance Assessment," in Proc. of 4th Int'l Workshop on Storage Network Architecture and Parallel I/Os (SNAPI), September 2007.

• Roger D. Chamberlain and Mark A. Franklin, "Automatic Deployment of Streaming Applications on Hybrid Architectures," in Proc. of 11th High Performance Embedded Computing Workshop (HPEC), September 2007.

• Roger D. Chamberlain and Berkley Shands, "Performance of Direct Attached Disk Subsystems," in Proc. of 11th High Performance Embedded Computing Workshop (HPEC), September 2007.

• Brandon Harris, Arpith C. Jacob, Joseph M. Lancaster, Jeremy Buhler, and Roger D. Chamberlain, "A Banded Smith-Waterman FPGA Accelerator for Mercury BLASTP," in Proc. of 17th Int'l Conf. on Field Programmable Logic and Applications (FPL), August 2007.

• Roger D. Chamberlain, Joseph Lancaster, and Ron K. Cytron, "Visions for Application Development on Hybrid Computing Systems." In Proc. of Reconfigurable Systems Summer Institute (RSSI), July 2007.

• Jeremy D. Buhler, Joseph M. Lancaster, Arpith C. Jacob, and Roger D. Chamberlain, "Mercury BLASTN: Faster DNA Sequence Comparison Using a Streaming Hardware Architecture." In Proc. of Reconfigurable Systems Summer Institute (RSSI), July 2007.

• Saurabh Gayen, Eric J. Tyson, Mark A. Franklin, and Roger D. Chamberlain, "A Federated Simulation Environment for Hybrid Systems." In Proc. of 21st Int'l Workshop on Principles of Advanced and Distributed Simulation (PADS), June 2007, pp. 198-207.

• Richard Hough, Praveen Krishnamurthy, Roger D. Chamberlain, Ron K. Cytron, John Lockwood, and Jason Fritts, "Empirical Performance Assessment Using Soft-Core Processors on Reconfigurable Hardware." In Proc. of Workshop on Experimental Computer Science (ExpCS), June 2007.

• Arpith Jacob, Joseph Lancaster, Jeremy Buhler, and Roger D. Chamberlain, "FPGA-accelerated seed generation in Mercury BLASTP." In Proc. of 15th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM), April 2007.

• Arpith Jacob, Joseph Lancaster, Jeremy Buhler, and Roger D. Chamberlain, "Preliminary results in accelerating profile HMM search on FPGAs." In Proc. of 6th IEEE International Workshop on High Performance Computational Biology, March 2007.

• Roger D. Chamberlain, Mark A. Franklin, and Ronald S. Indeck, "Exploiting Reconfigurability for Text Search." Presented at 10th High Performance Embedded Computing Workshop, September 2006. This research was performed while on leave at Exegy Inc.

• Patrick Crowley, Mark A. Franklin, Jeremy Buhler, and Roger D. Chamberlain, "Impact of CMP Design on High-Performance Embedded Computing." Presented at 10th High Performance Embedded Computing Workshop, September 2006.

• Saurabh Gayen, Eric J. Tyson, Mark A. Franklin, Roger D. Chamberlain, and Patrick Crowley, "X-Sim: A Federated Heterogeneous Simulation Environment." Presented at 10th High Performance Embedded Computing Workshop, September 2006.

• Benjamin C. Brodie, Roger D. Chamberlain, Berkley Shands, and Jason White, "Dynamic Reconfigurable Computing." In Proc. of 9th Military and Aerospace Programmable Logic Devices International Conference, September 2006. This research was performed while on leave at Exegy Inc.

• Rahul P. Maddimsetty, Jeremy Buhler, Roger D. Chamberlain, Mark A. Franklin, and Brandon Harris, "Accelerator Design for Protein Sequence HMM Search." In Proc. of 20th ACM Int'l Conference on Supercomputing, June 2006.

• Praveen Krishnamurthy, Roger D. Chamberlain, Ron K. Cytron, and Jason E. Fritts, "Evaluating Dusty Caches on General Workloads." In Proc. of 5th Workshop on Duplicating, Deconstructing, and Debunking, June 2006, pp. 9-16.

• Shobana Padmanabhan, Ron K. Cytron, Roger D. Chamberlain, and John W. Lockwood, "Automatic Application-Specific Microarchitecture Reconfiguration." In Proc. of 13th Reconfigurable Architectures Workshop, April 2006.

• Arpith Jacob, Brandon Harris, Jeremy Buhler, Roger D. Chamberlain, and Young H. Cho, "Scalable Softcore Vector Processor for Biosequence Applications." In Proc. of 14th IEEE Symposium on Field-Programmable Custom Computing Machines, April 2006, pp. 295-296.

• Gary Stiehr and Roger D. Chamberlain, "Improving Cluster Utilization through Intelligent Processor Sharing." In Proc. of Workshop on System Management Tools for Large-Scale Parallel Systems, April 2006.

• Roger D. Chamberlain, Ron K. Cytron, Jason E. Fritts, and John W. Lockwood, "Vision for Liquid Architecture." In Proc. of Next Generation Software Workshop, April 2006.

• Richard Hough, Phillip Jones, Scott Friedman, Roger Chamberlain, Jason Fritts, John Lockwood, and Ron Cytron, "Cycle-Accurate Microarchitecture Performance Evaluation." In Proc. of Workshop on Introspective Architecture, February 2006.

• Joseph Lancaster, Jeremy Buhler, and Roger D. Chamberlain, "Acceleration of Ungapped Extension in Mercury BLAST." In Proc. of 7th Workshop on Media and Streaming Processors, November 2005.

• Roger D. Chamberlain, "Embedding Applications within a Storage Appliance." Presented at 9th High Performance Embedded Computing Workshop, September 2005. This research was performed while on leave at Exegy Inc.

• Mark A. Franklin, Patrick Crowley, Roger D. Chamberlain, Jeremy Buhler, and James H. Buckley, "Application Development for Hybrid Pipelined Systems." Presented at 9th High Performance Embedded Computing Workshop, September 2005.

• Roger D. Chamberlain and Berkley Shands, "Streaming Data from Disk Store to Application." In Proc. of 3rd Int'l Workshop on Storage Network Architecture and Parallel I/Os, September 2005, pp. 17-23.

• S. Friedman, P. Krishnamurthy, R. Chamberlain, R. K. Cytron, J. E. Fritts, "Dusty Caches for Reference Counting Garbage Collection." In Proc. of Workshop on Memory Performance: Dealing with Applications, Systems and Architecture, September 2005. Also published in ACM SIGARCH Computer Architecture News, 34(1):3-10, March 2006.

• Roger D. Chamberlain, Steven Miller, Jason White, and Dan Gall, "Highly-Scalable Reconfigurable Computing." In Proc. of 8th Military and Aerospace Programmable Logic Devices International Conference, September 2005. This research was performed while on leave at Exegy Inc.

• Shobana Padmanabhan, Phillip Jones, David V. Schuehler, Scott J. Friedman, Praveen Krishnamurthy, Huakai Zhang, Roger Chamberlain, Ron K. Cytron, Jason Fritts, and John W. Lockwood, "Extracting and Improving Microarchitecture Performance on Reconfigurable Architectures." International Journal of Parallel Programming, 33(2-3):115-136, June 2005.

• Roger Chamberlain, John Lockwood, Saurabh Gayen, Richard Hough, and Phillip Jones, "Use of a Soft-Core Processor in a Hardware/Software Codesign Laboratory." In Proc. of Int'l Conf. on Microelectronic Systems Education, June 2005.

• Roger Chamberlain, Mark Franklin, Praveen Krishnamurthy, and Abhijit Mahajan, "VLSI Photonic Ring Multicomputer Interconnect: Architecture and Signal Processing Performance." Journal of VLSI Signal Processing, 40(1):57-72, May 2005.

• Daniel R. Fuhrmann, Lisandro Boggio, John Maschmeyer, and Roger Chamberlain, "Clutter Scattering Function Estimation and Ground Moving Target Detection from Multiple STAP Datacubes." In Proc. of IEEE Int'l Conf. on Acoustics, Speech, and Signal Processing, Vol. 5, March 2005, pp. 593-596.

• Roger Chamberlain and Ron K. Cytron, "Novel Techniques for Processing Unstructured Data Sets." In Proc. of IEEE Aerospace Conference, March 2005. This research was performed while on leave at Data Search Systems, Inc.

• Mark Franklin, Roger Chamberlain, Michael Henrichs, Berkley Shands, and Jason White, "An Architecture for Fast Processing of Large Unstructured Data Sets." In Proc. of 22nd Int'l Conf. on Computer Design, October 2004, pp. 280-287.

• Roger Chamberlain, Berkley Shands, and Jason White, "Achieving Real Data Throughput for an FPGA Co-Processor on Commodity Server Platforms." In Proc. of 1st Workshop on Building Block Engine Architectures for Computers and Networks, October 2004.

• Praveen Krishnamurthy, Jeremy Buhler, Roger Chamberlain, Mark Franklin, Kwame Gyang, and Joseph Lancaster, "Biosequence Similarity Search on the Mercury System." In Proc. of the IEEE 15th Int'l Conf. on Application-Specific Systems, Architectures and Processors, September 2004, pp. 365-375.

• Phillip Jones, Shobana Padmanabhan, David V. Schuehler, Scott J. Friedman, Praveen Krishnamurthy, Huakai Zhang, Roger Chamberlain, Ron K. Cytron, Jason Fritts, and John W. Lockwood, "Extracting and Improving Microarchitecture Performance on Reconfigurable Architectures." In Proc. of Workshop on Compilers and Tools for Constrained Embedded Systems, September 2004.

• David V. Schuehler, Benjamin C. Brodie, Roger D. Chamberlain, Ron K. Cytron, Scott J. Friedman, Jason Fritts, Phillip Jones, Praveen Krishnamurthy, John W. Lockwood, Shobana Padmanabhan, and Huakai Zhang, "Microarchitecture Optimization for Embedded Systems." Presented at 8th High Performance Embedded Computing Workshop, September 2004.

• Roger Chamberlain, Daniel R. Fuhrmann, John Maschmeyer, and Lisandro Boggio, "Parallel Matlab Computation for STAP Clutter Scattering Function Estimation and Moving Target Estimation." Presented at 8th High Performance Embedded Computing Workshop, September 2004.

• Roger D. Chamberlain, Jason E. Fritts, Praveen Krishnamurthy, and Hui Zhang, "Experimental Federated Modeling of an Optical Data Path." In Proc. of the 4th IASTED Int'l Conf. on Modelling, Simulation, and Optimization, August 2004, pp. 264-274.

• Qiong Zhang, Roger D. Chamberlain, Ronald S. Indeck, Benjamin West, and Jason White, "Massively Parallel Data Mining Using Reconfigurable Hardware: Approximate String Matching." In Proc. of Workshop on Massively Parallel Processing, April 2004.

• Benjamin West, Roger D. Chamberlain, Ronald S. Indeck, and Qiong Zhang, "An FPGA-based Search Engine for Unstructured Database." In Proc. of 2nd Workshop on Application Specific Processors, December 2003, pp. 25-32.

• Roger D. Chamberlain, Julius L. Goldstein, and Darko Ivanovich, "Implementation of Hearing Aid Signal Processing Algorithms on the TI DHP-100 Platform," in Proc. of 37th Asilomar Conf. on Signals, Systems and Computers, November 2003.

• Roger D. Chamberlain, Ron K. Cytron, Mark A. Franklin, and Ronald S. Indeck, "The Mercury System: Exploiting Truly Fast Hardware for Data Search." In Proc. of Int'l Workshop on Storage Network Architecture and Parallel I/Os, September 2003, pp. 65-72.

• Roger D. Chamberlain, Ron K. Cytron, Mark A. Franklin, and Ronald S. Indeck, "The Mercury System: Embedding Computation into Disk Drives." Presented at 7th High Performance Embedded Computing Workshop, September 2003.

• Praveen Krishnamurthy, Mark Franklin, and Roger Chamberlain, "Dynamic Reconfiguration of an Optical Interconnect." In Proc. of the 36th Annual Simulation Symp., April 2003, pp. 89-97.

• Roger Chamberlain, Eric Hemmeter, Robert Morley, and Jason White, "Modeling the Power Consumption of Audio Signal Processing Computations Using Customized Numerical Representations." In Proc. of the 36th Annual Simulation Symp., April 2003, pp. 249-255.

• Roger Chamberlain, Mark Franklin, and Ch'ng Shi Baw, "Gemini: An Optical Interconnection Network for Parallel Processing." IEEE Transactions on Parallel and Distributed Systems, 13(10):1038-1055, October 2002.

• Roger Chamberlain, Yen Hsiang Chew, Varuna DeAlwis, Eric Hemmeter, John Lockwood, Robert Morley, Ed Richter, Jason White, and Huakai Zhang, "Power Consumption of Customized Numerical Representations for Audio Signal Processing." Presented at 6th High Performance Embedded Computing Workshop, September 2002.

• Roger Chamberlain, Yen Hsiang Chew, Varuna DeAlwis, Eric Hemmeter, John Lockwood, Robert Morley, Ed Richter, Jason White, and Huakai Zhang, "Novel Numerical Representations for Low-Power Audio Signal Processing." Presented at Int'l Hearing Aid Research Conf., August 2002. The poster is available here.

• Roger D. Chamberlain, Mark A. Franklin, and Praveen Krishnamurthy, "Optical Network Reconfiguration for Signal Processing Applications." In Proc. of the IEEE Int'l Conf. on Application-Specific Systems, Architectures and Processors, July 2002, pp. 344-355.

• Michael D. DeVore, Roger D. Chamberlain, George L. Engel, Joseph A. O'Sullivan, and Mark A. Franklin, "Tradeoffs Between Quality of Results and Resource Consumption in a Recognition System." In Proc. of the IEEE Int'l Conf. on Application-Specific Systems, Architectures and Processors, July 2002, pp. 391-402.

• Roger Chamberlain, Ch'ng Shi Baw, Mark Franklin, Christopher Hackmann, Praveen Krishnamurthy, Abhijit Mahajan, and Michael Wrighton, "Evaluating the Performance of Photonic Interconnection Networks." In Proc. of the 35th Annual Simulation Symp., April 2002, pp. 209-218.

• Jason Fritts and Roger Chamberlain, "Breaking the Memory Bottleneck with an Optical Data Path." In Proc. of the 35th Annual Simulation Symp., April 2002, pp. 352-362.

• Roger D. Chamberlain, Mark A. Franklin, and Praveen Krishnamurthy, "Performance Evaluation of a Reconfigurable, Embedded Photonic Multiring Interconnection Network." In Proc. of 5th High Performance Embedded Computing Workshop, November 2001.

• Michael D. DeVore, Joseph A. O'Sullivan, Roger D. Chamberlain, and Mark A. Franklin, "Dependence of Recognition Accuracy on Available Network Bandwidth." In Proc. of 5th High Performance Embedded Computing Workshop, November 2001.

• Roger D. Chamberlain, Mark A. Franklin, and Abhijit Mahajan, "VLSI Photonic Ring Interconnect for Embedded Multicomputers: Architecture and Performance." In Proc. of the ISCA 14th Int'l Conf. on Parallel and Distributed Computing Systems, August 2001, pp. 351-358.

• J.L. Goldstein, M. Valente, and R.D. Chamberlain, "Acoustic and Psychoacoustic Benefits of Adaptive Compression Thresholds in Hearing Aid Amplifiers that Mimic Cochlear Function." J. Acoust. Soc. Am., 109:2355(A), 2001.

• Bradley L. Noble, J. Cris Wade, and Roger D. Chamberlain, "Performance Predictions for Speculative, Synchronous, VLSI Logic Simulation." In Proc. of the 34th Annual Simulation Symp., April 2001, pp. 56-64.

• Michael D. DeVore, Joseph A. O'Sullivan, Roger D. Chamberlain, and Mark A. Franklin, "Relationships Between Computational System Performance and Recognition System Performance." In Proc. of SPIE 15th Annual Int'l Symp. on Aerospace/Defense Sensing, Simulation and Controls (Automatic Target Recognition XI), April 2001.

• R.D. Chamberlain and David P. Discher, "Simbench: A Logic Simulation Benchmark Set." In Proc. of the Mentor User's Group Conf., October 2000.

• Joseph A. O'Sullivan, Mark A. Franklin, Michael D. DeVore, and Roger D. Chamberlain, "Analysis of Computational System Performance in Automatic Target Recognition." In Proc. of 4th High Performance Embedded Computing Workshop, September 2000.

• Abhijit Mahajan, M.A. Franklin, and R.D. Chamberlain, "Fairness Issues in an Embedded Photonic Ring Interconnect." In Proc. of 4th High Performance Embedded Computing Workshop, September 2000.

• J.L. Goldstein, M. Valente, R.D. Chamberlain, P. Gilchrist, and D. Ivanovich, "Pilot Experiments with a Simulated Hearing Aid Based on Models of Cochlear Compression." In Proc. of Int'l Hearing Aid Research Conf., August 2000.

• B.L. Noble and R.D. Chamberlain, "Analytic Performance Model for Speculative, Synchronous, Discrete-Event Simulation." In Proc. of 14th Workshop on Parallel and Distributed Simulation, June 2000, pp. 35-44.

• Ch'ng Shi Baw, R.D. Chamberlain, and M.A. Franklin, "Fair Scheduling in an Optical Interconnection Network." In Proc. of 7th Int'l Symp. on Modeling, Analysis, and Simulation of Computer and Telecommunications Systems, October 1999, pp. 56-65.

• Ch'ng Shi Baw, R.D. Chamberlain, M.A. Franklin, and M.G. Wrighton, "The Gemini Interconnect: Data Path Measurements and Performance Analysis." In Proc. of the 6th Int'l Conf. on Parallel Interconnects, October 1999, pp. 21-30.

• Ch'ng Shi Baw, R.D. Chamberlain, and M.A. Franklin, "Design of an Interconnection Network Using VLSI Photonics and Free-Space Optical Technologies." In Proc. of the 6th Int'l Conf. on Parallel Interconnects, October 1999, pp. 52-61.

• N.R. Jankowski, C. Bobcowski, D. Zipkin, R.R. Krchnavek, and R.D. Chamberlain, "MEMS-Based Optical Switch Design for Reconfigurable, Fault-Tolerant Optical Backplanes." In Proc. of the 6th Int'l Conf. on Parallel Interconnects, October 1999, pp. 149-156.

• T.D. Kimura, J.R. Gilman, R.A. Livingston, K. Chan, and R.D. Chamberlain, "Wireless Data Path for a Mobile, Modular Computer System." In Proc. of the 6th Int'l Conf. on Parallel Interconnects, October 1999, pp. 165-172.

• B.L. Noble and R.D. Chamberlain, "Performance Model for Speculative Simulation Using Predictive Optimism." In Proc. of 32nd Hawaii Int'l Conf. on System Sciences, January 1999. (Received Best Paper Award in the Software Technology Track.)

• R.D. Chamberlain, D. Chace, and A. Patil, "How Are We Doing? An Efficiency Measure for Shared, Heterogeneous Systems." In Proc. of the ISCA 11th Int'l Conf. on Parallel and Distributed Computing Systems, September 1998, pp. 15-21.

• R.D. Chamberlain, M.A. Franklin, R.R. Krchnavek, and B. Baysal, "Design of an Optically-Interconnected Multicomputer," In Proc. of 5th Int'l Conf. on Massively Parallel Processing Using Optical Interconnections, June 1998, pp. 114-122.

• W.A. Castellano, R.D. Chamberlain, and R.R. Krchnavek, "Optical Switching System for MPP, LAN, or WAN Systems." In Proc. of the 1997 IEEE Pacific Rim Conf. on Communications, Computers and Signal Processing, August 1997, pp. 260-264.

• G.D. Peterson and R.D. Chamberlain, "Parallel Application Performance in a Shared Resource Environment." Distributed Systems Engineering, 3:9-19, 1996.

• Y. Chen, B.L. Noble, and R.D. Chamberlain, "Comparing Edge-cuts to Communications Volume in Parallel VLSI Logic Simulation." In Proc. of the 8th IASTED Int'l Conf. on Parallel and Distributed Computing and Systems, October 1996, pp. 481-484.

• B.L. Noble and R.D. Chamberlain, "Performance of Speculative Computation in Synchronous Parallel Discrete-Event Simulation on Multiuser Execution Platforms." In Proc. of the 8th IASTED Int'l Conf. on Parallel and Distributed Computing and Systems, October 1996, pp. 489-494.

• G.D. Peterson and R.D. Chamberlain, "Parallel Processing the Easy Way: How to Do It and When It Works." Journal of Computers and Their Applications, 2(2), October 1995.

• R.R. Krchnavek, R.D. Chamberlain, T. Barry, V. Malhotra, and Z. Dittia, "Optical Interconnect Design for a Manufacturable Multicomputer." In Proc. of 2nd Int'l Conf. on Massively Parallel Processing Using Optical Interconnections, October 1995, pp. 279-288.

• B.L. Noble and R.D. Chamberlain, "Predicting the Future: Resource Requirements and Predictive Optimism." In Proc. of 9th Workshop on Parallel and Distributed Simulation, June 1995, pp. 157-164.

• R.D. Chamberlain, "Parallel Logic Simulation of VLSI Systems." In Proc. of 32nd Design Automation Conf., June 1995, pp. 139-143.

• G. Varghese, R.D. Chamberlain, and W.E. Weihl, "Deriving Global Virtual Time Algorithms from Conservative Simulation Protocols." Information Processing Letters, 54:121-126, 1995.

• R.D. Chamberlain and R.R. Krchnavek, "Optically Interconnected Multicomputers Using Inverted-Graph Topologies." IEEE Micro, 15(2):59-69, April 1995.

• R.D. Chamberlain, M.A. Franklin, G.D. Peterson, and M.A. Province, "Genetic Epidemiology, Parallel Algorithms, and Workstation Networks." In Proc. of 28th Hawaii Int'l Conf. on System Sciences, Vol. V, January 1995, pp. 101-110.

• B.L. Noble, G.D. Peterson, and R.D. Chamberlain, "Performance of Synchronous Parallel Discrete-Event Simulation." In Proc. of 28th Hawaii Int'l Conf. on System Sciences, Vol. II, January 1995, pp. 185-186.

• G.D. Peterson and R.D. Chamberlain, "Stealing Cycles: Can We Get Along?" In Proc. of 28th Hawaii Int'l Conf. on System Sciences, Vol. II, January 1995, pp. 422-431.

• G.D. Peterson and R.D. Chamberlain, "Sharing Networked Workstations: A Performance Model." In Proc. of 6th Symp. on Parallel and Distributed Processing, October 1994, pp. 308-315.

• M.A. Bailey, J.V. Briner, and R.D. Chamberlain, "Parallel Logic Simulation of VLSI Systems." ACM Computing Surveys, 26(3):255-294, September 1994.

• G.D. Peterson and R.D. Chamberlain, "Beyond Execution Time: Expanding the Use of Performance Models." IEEE Parallel & Distributed Technology, 2(2):37-49, Summer 1994.

• R.D. Chamberlain and C.L. Henderson, "Evaluating the Use of Pre-Simulation in VLSI Circuit Partitioning." In Proc. of 8th Workshop on Parallel and Distributed Simulation, July 1994, pp. 139-146.

• G. Varghese, R.D. Chamberlain, and W.E. Weihl, "The Pessimism Behind Optimistic Simulation." In Proc. of 8th Workshop on Parallel and Distributed Simulation, July 1994, pp. 126-131.

• R.D. Chamberlain and R.R. Krchnavek, "Topologies and Technologies for Optically Interconnected Multicomputers Using Inverted Graphs." In Proc. of 1st Workshop on Massively Parallel Processing Using Optical Interconnections, April 1994, pp. 255-265.

• G.D. Peterson and R.D. Chamberlain, "Performance Modeling Distributed Synchronous Iterative Algorithms." Tech. Rep. WUCCRC-94-03, February 1994.

• R.D. Chamberlain, "Inverted Graph Topologies for Optically Interconnected Multicomputers." Tech. Rep. WUCCRC-94-01, January 1994.

• G.D. Peterson and R.D. Chamberlain, "Exploiting Lookahead in Synchronous Parallel Simulation." In Proc. of Winter Simulation Conf., December 1993, pp. 706-712.

• R.D. Chamberlain and M.A. Franklin, "Performance Effects of Synchronization in Parallel Processors." In Proc. of 5th Symp. on Parallel and Distributed Processing, December 1993, pp. 611-616.

• R.D. Chamberlain and R.R. Krchnavek, "Architectures for Optically Interconnected Multicomputers." In Proc. of IEEE Global Telecommunications Conf., December 1993, pp. 1181-1186.

• G.D. Peterson and R.D. Chamberlain, "Performance of a Globally-Clocked Parallel Simulator." In Proc. of Int'l Conf. on Parallel Processing, Vol. III, August 1993, pp. 289-298.

• R.D. Chamberlain, "Fast Fourier Transform on a Hypercube Architecture Augmented with a Synchronization Network." Tech. Rep. WUCCRC-93-16, June 1993.

• E.E. Witte, R.D. Chamberlain, and M.A. Franklin, "Parallel Simulated Annealing Using Speculative Computation." IEEE Trans. on Parallel and Distributed Systems, 2(4):483-494, October 1991.

• R.D. Chamberlain and M.A. Franklin, "Analysis of Parallel Mixed-Mode Simulation Algorithms." In Proc. of Int'l Parallel Processing Symp., April 30-May 2, 1991, pp. 155-160.

• R.D. Chamberlain, "Gaussian Elimination on a Hypercube Architecture Augmented with a Synchronization Network." Tech. Rep. WUCCRC-91-12, April 1991.

• R.D. Chamberlain, "Potential Performance of Parallel Logic Simulation for Random and Heuristic Partitionings." Tech. Rep. WUCCRC-90-13, November 1990.

• R.D. Chamberlain, "Matrix Multiplication on a Hypercube Architecture Augmented with a Synchronization Network." Tech. Rep. WUCCRC-90-11, November 1990.

• E.E. Witte, R.D. Chamberlain, and M.A. Franklin, "Task Assignment by Parallel Simulated Annealing." In Proc. of Int'l Conf. on Computer Design, October 1990, pp. 74-77.

• R.D. Chamberlain and M.A. Franklin, "Hierarchical Discrete-Event Simulation on Hypercube Architectures." IEEE Micro, 10(4):10-20, August 1990.

• E.E. Witte, R.D. Chamberlain, and M.A. Franklin, "Parallel Simulated Annealing Using Speculative Computation." In Proc. of Int'l Conf. on Parallel Processing, Vol. III, August 1990, pp. 286-290.

• R.D. Chamberlain and M.A. Franklin, "Discrete-Event Simulation on Hypercube Architectures." In Proc. of Int'l Conf. on Computer-Aided Design, November 1988, pp. 272-275.

• R.D. Chamberlain, M.N. Edelman, M.A. Franklin, and E.E. Witte, "Simulated Annealing on a Multiprocessor." In Proc. of Int'l Conf. on Computer Design, 1988, pp. 540-544.

• R.D. Chamberlain and M.N. Edelman, "Lsim2 User's Manual." Tech. Rep. WUCS-88-3, January 1988.

• R.D. Chamberlain and M.A. Franklin, "A Unified Approach to Mixed-Mode Simulation." Tech. Rep. WUCS-86-20, November 1986.

• R.D. Chamberlain and M.A. Franklin, "Collecting Data About Logic Simulation." IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, CAD-5(3):405-412, July 1986.

• K.F. Wong, M.A. Franklin, R.D. Chamberlain, and B.L. Shing, "Statistics on Logic Simulation." In Proc. of 23rd Design Automation Conf., June 29-July 2, 1986, pp. 13-19.

• R.D. Chamberlain, "Lsim User Manual." Tech. Rep. WUCS-86-1, January 1986.

• R.D. Chamberlain, S. Husodo, and B.L. Shing, "Priority Queue Project." Tech. Rep. WUCCSD-85-14, December 1985.

Last modified 19 January 2012. Return to Roger's home page.

Roger Chamberlain <roger AT wustl.edu>